JESD204B vs. Serial LVDS Interface Considerations for Wideband Data Converter Applications

寬帶數據轉換器應用的JESD204B與串行LVDS接口考量

Abstract

摘要

The JESD204A/JESD204B industry standard for serial interfaces was developed to address the problem of interconnecting the newest wideband data converters with other system ICs in an efficient and cost saving manner. The motivation was to standardize an interface that would reduce the number of digital inputs/outputs between data converters and other devices, such as field programmable gate arrays (FGPAs) and system on a chip (SoC) devices through the use of a scalable high speed serial interface.

開發串行接口業界標準JESD204A/JESD204B的目的在于解決以高效省錢的方式互連最新寬帶數據轉換器與其他系統IC的問題。其動機在于通過采用可調整高速串行接口，對接口進行標準化，降低數據轉換器與其他器件（如現場可編程門陣列FPGA和系統級芯片SoC）之間的數字輸入/輸出數量。

Trends show that new applications, as well as advances in existing ones, are driving the need for wideband data converters with increasingly higher sampling frequencies and data resolutions. Transmitting data to and from these wideband converters poses a significant design problem as bandwidth limitations of existing I/O technologies force the need for higher pin counts on converter products. Consequently, systems’ PCB designs have become increasingly more complex in terms of interconnect density. The challenge is routing a large number of high speed digital signals while managing electrical noise. The ability to offer wideband data converters with GSPS sampling frequencies, using fewer interconnects, simplifies the PCB layout challenges, and allows for smaller form factor realization without impacting overall system performance.

趨勢顯示最新應用，以及現有應用的升級，正不斷需求采樣頻率和數據分辨率更高的寬帶數據轉換器。向這些寬帶轉換器傳送和獲取數據暴露了一個非常大的設計問題，即現有I/O技術帶寬的限制導致轉換器產品需要使用的引腳數更多。其結果便是PCB設計隨著互連密度的增加而更復雜。其挑戰在于進行大量高速數據信號走線的同時控制電噪聲，以及提供GSPS級別的寬帶數據轉換器采樣頻率的能力、使用更少的互連、簡化PCB布局難題并實現更小的尺寸，且不降低整體系統性能。

Market forces continue to press for more features, functionality, and performance in a given system, driving the need for higher data-handling capacity. The high speed analog-to-digital converter and digital-to-analog converter-to-FPGA interface had become a limiting factor in the ability of some system OEMs to meet their next generation data-intensive demands. The JESD204B serial interface specification was specifically created to help solve this problem by addressing this critical data link. Figure 1 shows typical high speed converter-to-FPGA interconnect configurations using JESD204A/JESD204B.

市場力量繼續施壓，要求給定系統擁有更多特性和功能以及更好的性能，推動了對更高數據處理能力的要求。高速模數轉換器和數模轉換器至FPGA接口已成為某些系統OEM廠商滿足下一代大量數據處理需要的限制因素。JESD204B串行接口規范專為解決這一關鍵數據鏈路的問題而建立。圖1顯示使用JESD204A/JESD204B的典型高速轉換器至FPGA互連配置。

Some key end-system applications that are driving the deployment of this specification, as well as a contrast between serial low voltage differential signaling (LVDS) and JESD204B, are the subject of the remainder of the article.

本文余下篇幅將探討推動該規范發展的某些關鍵的終端系統應用，以及串行低壓差分信號(LVDS)和JESD204B的對比。

Figure 1. Typical high speed converter to FGPA interconnect configurations using JESD204A/JESD204B interfacing (Source: Xilinx?).

圖1.使用JESD204A/JESD204B接口的典型高速轉換器至FGPA互連配置（來源：Xilinx?）。

The Applications Driving the Need for JESD204B

應用推動對JESD204B的需求

Wireless Infrastructure Transceivers

無線基礎設施收發器

OFDM-based technologies, such as LTE, used in today’s wireless infrastructure transceivers use DSP blocks implemented on FPGAs or SoC devices driving antenna array elements to generate beams for each individual sub- scriber’s handset. Each array element can require movement of hundreds of megabytes of data per second between FPGAs and data converters in both transmit or receive modes.

目前無線基礎設施收發器采用LTE等基于OFDM的技術，這類技術使用部署FPGA或SoC器件的DSP模塊，通過驅動天線陣列元件，單獨為每個用戶的手機產生波束。在發射和接收模式下，每個陣列元件每秒可能需要在FPGA和數據轉換器之間傳輸數百兆字節的數據。

Software-Defined Radios

軟件定義無線電

Today’s software-defined radios utilize advanced modulation schemes that can be reconfigured on the fly, and rapidly increasing channel bandwidths, to deliver unprecedented wireless data rates. Efficient, low power, low pin count FPGA-to-data converter interfaces in the antenna path play a critical role in their performance. Software-defined radio architectures are integral to the transceiver infrastructure for multicarrier, multimode wireless networks supporting GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA.

當今的軟件定義無線電技術利用先進的調制方案，可即時重配置，并極大地增加了通道帶寬，提供最佳的無線數據速率。天線路徑中高效、低功耗、低引腳數的FPGA至數據轉換器接口對性能起著決定性的作用。軟件定義無線電架構已與收發器基礎設施相整合，用于多載波、多模無線網絡，支持GSM、EDGE、W-CDMA、LTE、CDMA2000、WiMAX和TD-SCDMA。

Medical Imaging Systems

醫療成像系統

Medical imaging systems including ultrasound, computational tomography (CT) scanners, magnetic resonance imaging (MRI), and others generate many channels of data that flow through a data converter to FPGAs or DSPs. Continually increasing I/O counts are driving up the number   of components by requiring the use of interposers to match FPGA and converter pin out and increasing PCB complexity. This adds additional cost and complexity to the customer’s system that can be solved by the more efficient JESD204B interface.

醫療成像系統包括超聲、計算機斷層掃描(CT)的掃描儀、磁共振成像(MRI)等，這些應用產生很多通道的數據，流經數據轉換器至FPGA或DSP。I/O通道數的持續增長要求使用內插器匹配FPGA和轉換器的引腳輸出，迫使元件數增加，并使PCB復雜化。這加大了客戶系統的成本支出以及復雜程度；而這些問題可通過采用更有效的JESD204B接口加以解決。

Radar and Secure Communications

雷達和安全通信

Increasingly sophisticated pulse structures on today’s advanced radar receivers are pushing signal bandwidths toward 1 GHz and higher. Latest generation active electronically scaled array (AESA) radar systems may have thousands of elements. High bandwidth SERDES-based serial inter- faces are needed to connect the array element data converters to the FPGAs or DSPs that process incoming and generate outgoing data streams.

目前先進雷達接收器的脈沖結構日益復雜，迫使信號帶寬上升至1 GHz或更高。最新的有源電子調整陣列(AESA)雷達系統可能包含上千個元件。高帶寬SERDES串行接口用于連接陣列元件數據轉換器與FPGA或DSP，處理接收到的數據流，并將處理后產生的數據流發送出去。

Serial LVDS vs. JESD204B

串行LVDS與JESD204B的對比

Choosing Between Series LVDS and JESD204B Interface

在串行LVDS和JESD204B接口之間選擇 

In order to best select between converter products that use either LVDS    or the various versions of the JESD204 serial interface specification, a comparison of the features and capabilities of each interface is useful. A short tabular comparison is provided in Table 1. At the SERDES level, a notable difference between LVDS and JESD204 is the lane data rate, with JESD204 supporting greater than three times the serial link speed per lane when compared with LVDS. When comparing the high level features like multidevice synchronization, deterministic latency, and harmonic clocking, JESD204B is the only interface that provides this functionality. Systems requiring wide bandwidth multichannel converters that are sensitive to deterministic latency across all lanes and channels won’t be able to effectively use LVDS or parallel CMOS.

為了在使用LVDS和多種版本JESD204串行接口規范的轉換器產品間做出最佳選擇，對每種接口的特性和功能進行比較會非常有用。表1以簡單的表格形式對接口標準進行了對比。在SERDES級，LVDS和JESD204之間的顯著區別是通道數據速率，JESD204支持的每通道串行鏈路速率是LVDS的三倍以上。當比較諸如多器件同步、確定延遲和諧波時鐘等高級功能時，JESD204B是提供這些功能的唯一接口。所有通路和通道對確定延遲敏感、需要寬帶寬多通道轉換器的系統將無法有效使用LVDS或并行CMOS。

Table 1. Comparison Between Serial LVDS and JESD204 Specifications

表1.串行LVDS和JESD204規范對比

LVDS Overview

LVDS概述

LVDS is the traditional method of interfacing data converters with FPGAs or DSPs. LVDS was introduced in 1994 with the goal of providing higher bandwidth and lower power dissipation than the existing RS-422 and RS-485 differential transmission standards. LVDS was standardized with the publication of TIA/EIA-644 in 1995. The use of LVDS increased in the late 1990s and the standard was revised with the publication of TIA/EIA-644-A in 2001.

LVDS是連接數據轉換器與FPGA或DSP的傳統方法。LVDS于1994發布，目標在于提供比已有的RS-422和RS-485差分傳輸標準更高的帶寬和更低的功耗。隨著1995年TIA/EIA-644的發布，LVDS成為標準。二十世紀90年代末，LVDS的使用率上升，并隨著2001年TIA/EIA-644-A的發布，LVDS標準亦發布了修訂版。

LVDS uses differential signals with low voltage swings for high speed data transmission. The transmitter typically drives ±3.5 mA with a polarity matching the logic level to be sent through a 100 Ω resistor, generating a ±350 mV voltage swing at the receiver. The always-on current is routed in different directions to generate logic ones and zeros. The always-on nature of LVDS helps eliminate simultaneous switching noise spikes and potential electromagnetic interference that sometimes occur when transistors are turned on and off in single-ended technologies. The differential nature of LVDS also provides considerable immunity to common-mode noise sources. The TIA/EIA-644-A standard recommends a maximum data rate of 655 Mbps, although it predicts a possible speed of over 1.9 Gbps for an ideal transmission medium.

LVDS采用低電壓擺幅的差分信號，用于高速數據的傳輸。發射器驅動的電流典型值為±3.5 mA，通過100 Ω電阻發送極性匹配的邏輯電平，在接收器端產生±350 mV電壓擺幅。電流始終導通，并被路由至不同方向以便產生邏輯1和邏輯0。LVDS始終導通的特性有助于抑制同步開關噪聲尖峰和潛在電磁干擾——在單端技術中，晶體管的開關動作可能產生這些噪聲和干擾。LVDS差分的特征同樣提供了針對共模噪聲源的有效抑制。雖然在理想傳輸介質中，該標準預測速率可能超過1.9 Gbps，但TIA/EIA-644-A標準建議的最大數據速率為655 Mbps。

The huge increase in the number and speed of data channels between FPGAs or DSPs and data converters, particularly in the applications described earlier, has created several issues with the LVDS interface (see Figure 2). The bandwidth of a differential LVDS wire is limited to about 1.0 Gbps in the real world. In many current applications, this creates the need for a substantial number of high bandwidth PCB interconnects, each of which is a potential failure point. The large number of traces also increases PCB complexity or overall form factor, which raises both design and manufacturing costs. In some applications, the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth hungry applications.

FPGA或DSP與數據轉換器間數據通道和速度的大幅增長——尤其是前文討論的那些應用——使LVDS接口暴露了一些問題（見圖2）。現實中，差分LVDS線的帶寬限制在1.0 Gbps左右。在目前很多應用中，這一限制導致需要許多高帶寬PCB互連，而每一處都有可能出故障。大量的走線還增加了PCB的復雜性或整體尺寸，導致設計和制造成本上升。在某些帶寬需求量巨大的應用中，數據轉換器接口已成為滿足所需系統性能的制約因素。

Figure 2. Challenges in system design and interconnect using parallel CMOS or LVDS.

圖2.使用并行CMOS或LVDS帶來的系統設計與互連的挑戰。

JESD204B OVERVIEW

JESD204B概述

The JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology with the goal of providing a higher speed serial interface for data converters to increase bandwidth and reduce the number of digital inputs and outputs between high speed data converters and other devices. The standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock, enabling single line pair communications at a much higher speed.