AD9557/PCBZ，AD9557 的評估板是一款低環路帶寬
時鐘乘法器，可為許多系統（包括同步
光纖網絡 (OTN/SONET/SDH)）提供抖動清除和同步。 AD9557 生成與最多四個外部輸入參考同步的輸出時鐘。數字 PLL 可以減少與外部參考相關的輸入時間抖動或
相位噪聲。即使所有參考輸入均出現故障，AD9557 的數控環路和保持
電路也會持續生成低抖動輸出時鐘
說明
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AD9557/PCBZ, Evaluation Board for the AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9557 continuously generates a low jitter output clock even when all reference inputs have failed
主要特色
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Operating Frequency
0.002 to 1250 MHz
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